![]() ![]() ![]() Mishra (2012) Characteristic comparison of connected DG FINFET, TG FINFET and Independent Gate FINFET on 32 nm technology. Mishra, Optimization of Pie-gate Bulk FinFET Structure. In: Proc 30th IEEE European Solid-State Circuits Conference, pp 69–72. Chuang (2004) FinFET SRAM for high-performance low-power applications. In: IEEE International Memory Workshop, pp 1–4. Ganguly (2015) A Bulk Planar SiGe Quantum-Well Based ZRAM with Low V T Variability. In: Annual IEEE India Conference, pp 1–4. Kaur (2015) Investigation of short channel effects in Bulk MOSFET and SOI FinFET at 20nm node technology. Colinge, Multigate transistors as the future of classical metal-oxide semiconductor field-effect transistors. Colinge, FinFETs and OtherMulti-Gate Transistors (Springer, New York, 2008) Bondyopadhyay, Moore’s law governs the silicon revolution. In addition to this, subthreshold swing close to industry standard has been attained in single gate and dual-k material heterojunction SOI FinFET structure. Low value of DIBL has been attained in heterojunction structures with least value of 29.15 mV/V for dual-k heterojunction SOI FinFET, which depicts its endurance towards short channel effects. The single gate material and dual-k gate dielectric material heterojunction SOI FinFET has a high I on to I off ratio of 9 × 10 4. Performance parameters, such as I on(on current), I off (off current), I on-I off ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), which are important at nanoscale technology, have been evaluated for comparison of the three structures. Conventional and two heterojunction structures with different gate dielectric material stacks have been designed and simulated with TCAD. Novel Si/SiGe homojunction and heterojunction channel silicon on insulator (SOI) fin field-effect transistor at 14 nm gate length has been delineated in the research article. ![]()
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